Electronic devices have conventionally adopted various kinds of communications means to communicate with various kinds of electronic devices. In the era when the communications means worked at low speed, every electronic device had its own communications circuit, and a communications circuit was accessible only to one electronic device; communication was carried out on a one-to-one basis.
Recent years have seen dramatic improvements in operating speed of those circuits, enabling many electronic devices to access a single communications circuit.
FIG. 7 shows such an example, where USB (Universal Serial Bus) can connect up to 127 devices to a single host. Each device is equipped with up to 16 end points. This means that the host is required have a capability to communicate with as many as 127×16=2032 end points.
Now, referring to FIG. 8, conventional communications control units (host circuits) will be described. A communications control unit includes a CPU 101, a ROM 102, various I/O devices 103, and a communications control circuit 105. The CPU 101, ROM 102, and I/O devices 103 are connected to the communications control circuit 105 via a CPU address bus and a CPU data bus.
The communications control circuit 105 includes a communications controller 50, channel “0” FIFO 510 to channel “n” FIFO 51n provided for respective channels, an information register 54, a reception circuit 55, a transmission circuit 56, a channel selector 57, and a FIFO control circuit 58.
The channel FIFOs 510 to 51n each include RAM, a read counter 520 to 52n, and a write counter 530 to 53n.
The CPU 101 controls the I/O devices 103 and the communications control circuit 105 according to a program stored in the ROM 102. The I/O devices 103 may be, for example, a keyboard, a display, a data memory, a motor, and a sensor.
The following will describe procedures to transmit data from channel “0” to the communications bus using the communications control circuit 105 sequentially.
(1) The CPU 101 writes communications data from the CPU data bus to the channel “0” FIFO 510.
(2) The write counter 530 inside the channel “0” FIFO 510 is incremented each time a set of communications data is written to the FIFO 510. When the write counter 530 reaches the same value as the read counter 520, the FIFO 510 is full and stops writing. The read and write counters 520 to 52n , 530 to 53n in the FIFOs 510 to 51n are all endless counters. If they are rated for 64 bites, for example, they change from 0 to 63 and then start all over again from 0. The counting may start from any given value, but is required to end in such a manner that the values of the read counters 520 to 52n are equal to those of the write counter 530 to 53n.
(3) The CPU 101 writes communications speed, type, validity, and other information on the channel “0” to the information register 54.
(4) The communications controller 50 checks the value in the information register 54 and the conditions of the channel “0” FIFO 510 to the channel “n” FIFO 51n, while incrementing the channel number from 0 to n sequentially, so as to see whether a preparation has been done for a communication.
(5) Upon determination that the channel “0” is ready, the communications controller 50 instructs the transmission circuit 56 to start transmission.
(6) When the transmission circuit 56 sends the FIFO control circuit 58 a transmission data request, the FIFO control circuit 58 reads data from the channel “0” FIFO 510 and sends it to the transmission circuit 56 via the channel selector 57. The read counter 520 is incremented each time a set of data is read out from the channel “0” FIFO 510. When the read counter 520 reaches the same value as the write counter 530, the FIFO 510 is empty.
(7) The transmission circuit 56 sends the data to the communications bus.
(8) Steps (6) and (7) are repeated until there is no more data to send (until the FIFO 510 is empty).
(9) When the FIFO is empty, the operation returns to (1), whereupon a process for a next channel is carried out.
The following will describe procedures to receive data from a communications bus to the channel “1” using the communications control circuit 105.
(1) The CPU 101 writes communications speed, type, and other information on the channel “1” to the information register 54.
(2) The reception circuit 55 receives data to be transmitted to the channel “1” from the communications bus.
(3) The communications controller 50 checks the received data for the channel to which the data is directed and sets the channel number to 1.
(4) When the reception circuit 55 sends the FIFO control circuit 58 a reception data request, the FIFO control circuit 58 sends a writing signal to the channel “1” FIFO 511 and writes the reception data to the channel “1” FIFO 511. The write counter 531 is incremented each time a set of data is written to the channel “1” FIFO 511.
(5) When all data is received (for example, the FIFO is full, a predetermined number of sets of data is received, or a reception termination signal is received), the CPU 101 reads data from the channel “1” FIFO 511 and transmits it to the CPU data bus. The read counter 521 is incremented each time a set of data is read. When the read counter 521 reaches the same value as the write counter 531, the FIFO is empty.
(6) When the FIFO is empty, the operation returns to (1), whereupon a process for a next channel is carried out.
The communications control circuit detailed in the foregoing requires as many FIFOs, hence read counters, write counters, and FIFO-use memories (RAM), as communications channels. The capacity of the FIFO memory (RAM) needs to be greater than or equal to a maximum communications data packet size.
For example, a USB connection, handling 2032 channels and a maximum packet size of 1023 bites, requires a large-scale circuit and large-capacity memory: 2032 read counters, 2032 write counters, and 2032 FIFO memories (RAM) each storing 1023 bites (which adds to 1023 bites×2032=2078736 bites).
If there has occurred an error during a transmission, the CPU 101 needs to once again write the same data to the FIFOs and instruct the transmission circuit 56 to start transmission; if there has occurred an error during a reception, the CPU 101 needs to discard the data in the FIFOs and once again receive the same data. If these restarting processes are to be carried out by the communications control circuit 105, instead of the CPU 101, every FIFO needs to be equipped with a circuit which records the communications-starting values of the read and write counters in the FIFO and on the occurrence of an error during communications, writes the recorded values back to the read and write counters. The provision of the circuit further adds to the complexity of the circuit.
The easiest way to reduce circuit complexity is to adopt the configuration shown in FIG. 9 (conventional example 2). The communications control unit arranged as in the figure includes a CPU 201, a ROM 202, various I/O devices 203, a work RAM 61, a reception circuit 62, a transmission circuit 63, and a DMA controller 64 which are connected via a CPU address bus and a CPU data bus.
The work RAM 61 stores communications data, addresses, the numbers of sets of data, and information. The DMA controller 64 has a DMA transfer request controller 640, an address counter 641, and a data set counter 642.
In this arrangement, the CPU 201 stores all of data, an address, the number of sets of data, and information for each channel in the work RAM 61 and transfers data from the work RAM 61 to the reception circuit 62 and the transmission circuit 63 and vice versa via the CPU data bus using the DMA controller 64.
The CPU 201 controls the I/O devices 203, the work RAM 61, the reception circuit 62, the transmission circuit 63, and the DMA controller 64 according to a program stored in the ROM 2.
Data is transmitted by the following procedures.
(1) The CPU 201 writes data to the work RAM 61.
(2) The CPU 201 checks the number of sets of data in the work RAM 61, communications speed, type, validity, and other information to determine whether a preparation has been done for a transmission.
(3) Upon determination that a preparation has been done for a transmission, the CPU 201 sets the address counter 641 and the data set counter 642 in the DMA controller 64 to the address and number of sets of data in the work RAM 61 storing the data, and instructs the transmission circuit 63 to start transmission.
(4) When the transmission circuit 63 sends the DMA transfer request controller 640 in the DMA controller 64 a transmission data request, the DMA controller 64 sends that specific address to the CPU address bus, reads corresponding data from the work RAM 61, and transfers the data to the transmission circuit 63 via the CPU data bus. The DMA controller 64 increments the address counter 641 and decrements the data set counter 642 each time a set of data is transferred.
(5) The transmission circuit 63 sends the data readout from the work RAM 61 to the communications bus.
(6) Steps (4) and (5) are repeated until there is no more data (until the data set counter 642 shows a 0 value).
(7) When there is no more data, the operation returns to (1), whereupon a process for a next channel is carried out.
Data is received by the following procedures.
(1) The CPU 201 writes, for example, the address and number of sets of data in, and information on, the work RAM 61 storing reception data to the work RAM 61.
(2) The reception circuit 62 receives data addressed to the channel “1” from the communications bus.
(3) The CPU 201 checks a channel for the received data, and also checks information on, and the number of sets of data for, the channel “1”. Upon determination that a preparation has been done for a reception, the CPU 201 sets the address counter 641 and the data counter 642 in the DMA controller 64 to an address and the number of sets of data.
(4) When the reception circuit 62 sends the DMA transfer request controller 640 in the DMA controller 64 a reception data request, the DMA controller 64 sends that specific address to the CPU address bus, reads data from the reception circuit 62, and transfers the data to the work RAM 61 via the CPU data bus. The DMA controller 64 increments the address counter 641 and decrements the data set counter 642 each time a set of data is transferred.
(5) When all data is received (for example, the data set counter 642 shows a 0 value, a predetermined number of sets of data is received, or a reception termination signal is received), the operation is ended.
(6) When all data is received, the operation returns to (1), whereupon a process for a next channel is carried out.
In this method, all data to be transmitted and received is stored in the work RAM 61, it suffices to set aside part of the work RAM 61 for channels through which communications is actually being carried out. Additionally, the address counter 641 and the data set counter 642 in the DMA controller 64 are commonly used for all the channels. These factors greatly reduce circuit complexity.
The CPU 201, however, needs to write values to the address counter 641 and the data set counter 642 in the DMA controller 64 for each communication, as well as to instruct the transmission circuit 63 for transmission and instantly react to a request from the reception circuit 62. To this end, the CPU 201 needs to have very high performance to carry out high speed communications
If there has occurred an error during a transmission, the CPU 201 needs to write values to the address counter 641 and the data set counter 642 in the DMA controller 64 and instruct the transmission circuit 63 for transmission, so as to transmit the same data again; if there has occurred an error during a reception, the CPU 201 needs to write values to the address counter 641 and the data set counter 642 in the DMA controller 64 and wait for incoming data, so as to receive the same data. This demonstrates that the CPU 201 needs to operate on the occurrence of an error too.
In addition, during a data transfer, the DMA controller 64 uses the CPU address bus and the CPU data bus, inhibiting the CPU 201 from functioning. This results in poor control over the I/O devices 203.
Japanese Unexamined Patent Application 2-32650/1990 (Tokukaihei 2-32650, published on Feb. 2, 1990) discloses an approach to these problems, using common memory and a CPU, other than the CPU 201, which performs communications, as in conventional example 3 in FIG. 10 of the document.
In this example, the communications control unit includes a CPU 301, a ROM 302, various I/O devices 303, a common work RAM 71, a common memory 72, a reception circuit 73, a transmission circuit 74, a DMA controller 75, a CPU 70, and a ROM 76.
The CPU 301, ROM 302, I/O devices 303, common work RAM 71, and common memory 72 are connected to a CPU address bus and a CPU data bus. The CPU 70, common work RAM 71, common memory 72, reception circuit 73, transmission circuit 74, DMA controller 75, and ROM 76 are connected to a CPU 70 address bus and a CPU 70 data bus.
The CPU 301 controls the I/O devices 303, common work RAM 71, and common memory 72 according to a program stored in the ROM 302. The CPU 70 controls the common work RAM 71, common memory 72, reception circuit 73, transmission circuit 74, and DMA controller 75 according to a program stored in the ROM 76.
Data is transmitted by the following procedures.
(1) The CPU 301 writes data to the common work RAM 71 and also writes, for example, the address of the data, the number of the sets of the data, and other information to the common memory 72.
(2) The CPU 70 checks the number of the sets of the data, as well as communications speed, type, validity, other information, etc. in the common memory 72 to determine whether a preparation has been done for a transmission.
(3) Upon determination that a preparation has been done for a transmission, the CPU 70 sets the address counter 751 and the data set counter 752 in the DMA controller 75 to the address and number of sets of the data in the common work RAM 71 storing the data, and instructs the transmission circuit 74 to start transmission.
(4) When the transmission circuit 74 sends the DMA transfer request controller 750 in the DMA controller 75 a communications data request, the DMA controller 75 sends that specific address to the CPU 70 address bus, reads corresponding data from the common work RAM 71, and transfers the data to the transmission circuit 74 via the CPU 70 data bus. The DMA controller 75 increments the address counter 751 and decrements the data set counter 742 each time a set of data is transferred.
(5) The transmission circuit 74 sends data to the communications bus.
(6) Steps (4) and (5) are repeated until there is no more data (until the data set counter 752 shows a 0 value).
(7) When there is no more data, the operation returns to (1), whereupon a process for a next channel is carried out.
Data is received by the following procedures.
(1) The CPU 301 writes, for example, the address and number of sets of, and information on, the data in the common work RAM 71 storing reception data to the common memory 72.
(2) The reception circuit 73 receives data addressed to the channel “1” from the communications bus.
(3) The CPU 70 checks a channel for the received data, and also information on, and the number of sets of data for, the channel “1”. Upon determination that a preparation has been done for a reception, the CPU 70 sets the address counter 751 and the data set counter 752 in the DMA controller 75 to an address and the number of sets of data.
(4) When the reception circuit 73 sends the DMA transfer request controller 750 in the DMA controller 75 a reception data request, the DMA controller 75 sends that specific address to the CPU 70 address bus, reads data from the reception circuit 73, and transfers the data to the common work RAM 71 via the CPU 70 data bus. The DMA controller 75 increments the address counter 751 and decrements the data set counter 752 each time a set of data is transferred.
(5) When all data is received (for example, the data set counter shows a 0 value, a predetermined number of sets of data is received, or reception termination signal is received), the operation is ended.
(6) When all data is received, the operation returns to (1), whereupon a process for a next channel is carried out.
The approach assigns communications control, data transfer, etc. to the CPU 70, thereby dedicating the CPU 301 to the control of the I/O devices 303.
The CPU 70, however, needs to write values to the address counter 751 and the data set counter 752 in the DMA controller 75 for each communication, as well as to instruct the transmission circuit 74 for transmission and instantly react to a request from the reception circuit 73. To this end, the CPU 70 needs to have very high performance to carry out high speed communications.
If there has occurred an error during a transmission, the CPU 70 needs to write values to the address counter 751 and the data set counter 752 in the DMA controller 75 and instruct the transmission circuit 74 for transmission, so as to transmit the same data again; if there has occurred an error during a reception, the CPU 70 needs to write values to address counter 751 and the data set counter 752 in the DMA controller 75 and wait for incoming data, so as to receive the same data. This demonstrates that the approach makes no difference at all regarding the fact that the CPU 70 needs to operate on the occurrence of an error too.
In addition, the approach generally requires complex CPUs and program-storing ROM. Circuit complexity is considerable high when compared to FIG. 9.
For example, Japanese Unexamined Patent Application 62-60044/1987 (Tokukaisho 62-60044, published on Mar. 16, 1987) is an attempt to achieve high speed communications through use of more CPUs, one for transmission control and another for reception control, but is accompanied by the problem of increased circuit complexity.